library ieee;
use ieee.std_logic_1164.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use ieee.numeric_std.all;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

package ssd_controller_pkg is
    component ssd_controller is
        generic (
            -- cycle constants
            CYCLES_TOTAL     : integer := 16e5; -- 16 ms / 10 ns
            CYCLES_PER_ANODE : integer := 4e5; -- 16e5 / 4
            -- segment enables (anode signals)
            SEG_LOW : integer := 0;
            SEG_HIGH : integer := 3;
            -- individual segments
            SEG_MIN : integer := 0;
            SEG_MAX : integer := 6
        );
        port (
            clk : in std_logic;
            res : in std_logic;

            tick     : in std_logic;
            cnt_secs : in integer;

            seg_n : out std_logic_vector(SEG_MAX downto SEG_MIN);
            dp_n : out std_logic;
            an_n : out std_logic_vector(SEG_HIGH downto SEG_LOW)
        );
    end component;
end package;
